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iverilog

Preprocess and compile Verilog HDL (IEEE-1364) code into executable programs for simulation. tldr-pages

On several platforms

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Several platforms

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Compile a source file into an executable

iverilog path/to/source.v -o path/to/executableIdentify

Compile a source file into an executable while displaying all warnings

iverilog path/to/source.v -Wall -o path/to/executableIdentify

Compile and run explicitly using the VVP runtime

iverilog -o path/to/executable -tvvp path/to/source.vIdentify

Compile using Verilog library files from a different path

iverilog path/to/source.v -o path/to/executable -Ipath/to/library_directoryIdentify

Preprocess Verilog code without compiling

iverilog -E path/to/source.vIdentify